1. Technical Field
The present invention relates generally to integrated circuits, and more particularly, to integrated circuits having a high-voltage input/output driver/receiver.
2. Description of the Related Art
Input/output (I/O) drivers interconnect integrated circuits in larger circuits and systems. High-voltage I/O drivers are used in designs wherein an I/O pin of an integrated circuit may experience voltages higher than the power supply rail supplying output driver transistors. High-voltage I/O driver/receivers must be designed to operate in the presence of these higher voltages.
Power management systems in computers, personal digital assistants (PDAs) and other battery powered or power sensitive applications may selectively power-down portions of the electronics. When an integrated circuit is powered down, other integrated circuits may still be powered and may impress voltages on the pins of the powered-down integrated circuit. These voltages can cause damage to the transistors within the integrated circuit, not only by excessive current that may destroy the transistors causing failure of the integrated circuit, but by over-stressing the transistors with gate-to-source voltages in excess of safe margins.
Over-stressing a transistor reduces the mean-time-before-failure (MTBF) of the transistor and therefore the MTBF of the overall integrated circuit. Since an individual I/O driver/receiver circuit may be repeated hundreds of times within an integrated circuit and output driver transistors typically contribute greatly to the overall reliability equation, the MTBF is dramatically affected by the design of I/O driver/receivers.
Over-stressing a transistor over time also causes changes in the threshold voltage of the transistor. Changes in the threshold voltage of an output driver transistor affect the switching point of the transistor and therefore the transition time and propagation delay of the output.
In light of the foregoing, it would be desirable to provide a method and apparatus for enhancing the reliability of a high voltage I/O driver/receiver. It would further be desirable to provide a method and apparatus that reduce variations in the transition time and propagation delay of an output driver.
The objective of enhancing the reliability of a high-voltage I/O driver/receiver and reducing variations in propagation delay and transition time are accomplished in a method and apparatus that reduce stresses in I/O driver/receiver transistors when power is removed from a power supply rail. The circuit has a control transistor coupled to an I/O pad of the I/O driver/receiver for isolating one or more transistors within the I/O driver/receiver and a bias network coupled to the gate of the control transistor and also coupled to the I/O pad so that the bias network produces a bias for the control transistor one diode drop or less from the voltage on the I/O pad.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.